1. Field
The disclosed technology relates to semiconductor technology, and particularly, to a FinFET and a method for manufacturing the same.
2. Description of the Related Technology
With size reduction of planar-type semiconductor devices, short-channel effect becomes increasingly obvious. In order to address problems caused by the short channel effect, three-dimensional semiconductor devices such as Fin Field Effect Transistors (FinFETs) have been proposed. The FinFET comprises a semiconductor fin forming a channel region and a gate stack covering at least a sidewall of the semiconductor fin. The gate stack intersects the semiconductor fin and comprises a gate conductor and a gate dielectric. The gate dielectric isolates the gate conductor from the semiconductor fin. The FinFET may have a double-gate, a tri-gate, or an annular-gate configuration. The semiconductor fin has a small width (i.e., thickness), and thus the FinFET can improve control of carriers in the channel region by the gate conductor and suppress the short-channel effect. Conventional processes for manufacturing the gate stack comprises depositing a dielectric layer and a conductive layer and then forming a pattern of the gate stack through photolithography. However, with the size reduction of the devices, it becomes increasingly difficult to form a gate with a small size (i.e., gate length) along a length direction of the semiconductor fin.
Therefore, it is desired to provide a method for manufacturing a semiconductor device with a small gate size.